A quantitative architecture study using SimpleScalar to optimize cache, branch prediction and pipeline design under a strict 512-byte hardware budget.
I'm a Computer Engineering student at Information Technology University, Lahore, and a software-first builder who's just as comfortable down at the metal. My work spans two things that don't usually sit in the same portfolio: AI-driven software — chatbots, voice automation, workflow systems — and embedded/computer-architecture engineering, from STM32 firmware to processor simulation in SimpleScalar and RISC-V pipeline design.
What connects the two is the same underlying instinct: I want to know what a system is actually doing, whether that's a cache miss or a webhook payload. I don't treat "software" and "hardware" as separate tracks — they're both just systems, and the discipline of debugging one sharpens the other. I'd rather be the engineer who can trace a race condition in an AI pipeline in the morning and a UART timing issue in the afternoon.
Going forward, I'm looking for software engineering, AI/automation engineering, or full-stack roles where I can keep shipping real systems — with my embedded and architecture background as a genuine differentiator, not the whole story.
Professionally, I spent from July 2025 to April 2026 at ByteForce IT Solutions as a Web & Automation Developer, where I designed and deployed conversational AI systems — chatbots handling customer support and order queries, AI voice/calling bots automating outbound and inbound calls, and n8n pipelines connecting websites, CRMs, and messaging platforms so businesses could stop doing repetitive work by hand. I also built and shipped WordPress and WooCommerce sites end-to-end, from theming to performance tuning.
Paid and internship work, applying the same engineering discipline to real deliverables.
Formal study, grounded by the same hands-on systems work shown throughout this site.
Organizations I contribute to outside the lab.
Grouped by the layer of the stack each tool operates on — hardware up to application.
A collection of systems spanning AI & automation, embedded firmware, computer architecture, software engineering, and analog electronics.
A quantitative architecture study using SimpleScalar to optimize cache, branch prediction and pipeline design under a strict 512-byte hardware budget.
A 32-bit RISC-V CPU rebuilt from single-cycle to a fully pipelined 5-stage datapath in Verilog HDL, with hazard-safe forwarding and stalling.
An end-to-end MATLAB pipeline classifying real clinical EEG epochs into five sleep stages at 92.6% accuracy.
An industrial-style SCADA master-slave network over RS485, with EEPROM-backed historical logging surviving power loss.
An enterprise-modeled distribution management platform with a Qt GUI and JSON persistence, scoring top 5% in academic evaluation.
A rental management platform using the Gale–Shapley stable matching algorithm to fairly pair tenants with properties.
A biomedical DSP pipeline turning raw clinical ECG recordings into heart-rate estimates and rule-based abnormality classification.
An LLM-backed chatbot handling customer support and order queries across business websites, built for real ByteForce clients.
An automated inbound/outbound voice calling system combining speech, LLM reasoning and telephony automation for client outreach.
FFT/FIR-based denoising and automated trend detection applied to real AAPL price time-series.
A deterministic real-time sensing-to-actuation loop on STM32F4, driven entirely by timers and interrupts.
A set of n8n pipelines connecting client websites, CRMs and messaging platforms to remove repetitive manual work.
A C++ system automating restaurant workflows end-to-end, from order intake through kitchen sequencing to delivery.
A low-noise BJT preamplifier engineered for stable gain across the full audio band, validated against oscilloscope measurement.
A K-map-minimized combinational controller managing industrial tank outlet logic with built-in fault detection.
WordPress and WooCommerce websites built end-to-end for real clients — theming, plugin integration and performance tuning.
A closed-loop analog temperature controller using thermistor sensing and MOSFET-driven bidirectional actuation.
A purely combinational 8-key smart-home appliance controller with safety interlocks — no flip-flops allowed.
A MATLAB visualization of how the complex map w = z² + z warps a uniform spatial grid in real time.
A 2D-interpolation pipeline upsampling coarse temperature sensor data into a 10× higher-resolution thermal map.
A fully analog, low-cost solar battery charger regulating a stable ~6V output for off-grid use.
An automatic dusk-to-dawn LED street light controller switching purely on ambient light via an LDR and MOSFET.
ISMS fundamentals, risk assessment and security controls, ISO 27001:2022 standards, cybersecurity governance, and real-world security scenarios.
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