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Computer Architecture

5-Stage Pipelined RISC-V Processor

A 32-bit RISC-V CPU rebuilt from single-cycle to a fully pipelined 5-stage datapath in Verilog HDL, with hazard-safe forwarding and stalling.

Difficulty — expert Complexity — 9/10 Category — Computer Architecture
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Overview

This project takes a working single-cycle RISC-V processor and re-architects it into a pipelined design capable of executing multiple instructions concurrently. The goal wasn't just 'make it faster' — it was to prove the pipeline is functionally identical to the single-cycle baseline under every hazard condition, verified cycle-by-cycle in simulation.

Architecture

A modular datapath — ALU, register file, instruction/data memory, shifter, sign extender and control unit — connected through four dedicated pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB), with control signals redesigned to propagate correctly across every stage boundary.

Key Features

  • Full RISC-V instruction subset: arithmetic, logical, shift, comparison, load/store and conditional branch instructions.
  • Forwarding paths and pipeline stalling to resolve data hazards without corrupting instruction results.
  • Propagation-delay modeling in hardware modules to emulate realistic timing behavior, not just functional correctness.
  • Custom diagnostic assembly programs exercising every instruction category.

Development Process

  • Implemented and fully verified the single-cycle processor first, establishing a correctness baseline.
  • Inserted pipeline registers between stages and re-routed control signal propagation to match.
  • Added hazard detection, then forwarding and stalling logic, re-testing after each addition.
  • Compared pipelined vs. single-cycle cycle time and throughput to quantify the improvement.

Challenges & Solutions

Challenge

Redesigning control-signal timing for a pipeline is easy to get functionally 'close' but subtly wrong — signals can arrive at the correct value but the wrong cycle.

Solution

Verified every control signal against cycle-accurate waveforms rather than trusting final register values alone.

Challenge

Data hazards from back-to-back dependent instructions could silently corrupt results if forwarding paths missed a case.

Solution

Built targeted diagnostic assembly programs specifically to trigger every hazard class, not just general-purpose test code.

Results & Impact

The pipelined design executes multiple instructions concurrently while remaining functionally identical to the single-cycle baseline across every tested hazard scenario, demonstrating a measurable throughput improvement from instruction-level parallelism.

Future Improvements

  • Add branch prediction to reduce control-hazard stalls.
  • Extend the ISA subset supported.
  • Port the verified RTL toward FPGA synthesis.